1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to an in-plane switching mode (IPS) LCD and fabricating method thereof.
2. Discussion of the Related Art
Until recently, display devices generally employed cathode-ray tubes (CRTs). Presently, many efforts are being made to study and develop various types of flat panel displays, such as liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), and electro-luminescence displays (ELDs), as substitutions for CRTs.
Of these flat panel displays, the LCD has high resolution images, lightness, thin profile, compact size, and low voltage power supply requirements.
In general, a vertical alignment mode (VA) LCD has been employed. The VA LCD includes two substrates that are spaced apart and face each other, and a liquid crystal material layer interposed between the two substrates. Each of the two substrates includes electrodes that face each other, wherein a voltage supplied to each of the electrodes induces an electric field to the liquid crystal material layer. Accordingly, alignment of liquid crystal molecules of the liquid crystal material layer is changed by varying an intensity or direction of the induced electric field, thereby changing light transmissivity through the liquid crystal material layer. Thus, the VA LCD displays images by varying the induced electric field. However, since the VA LCD is driven by the induced electric field between the two substrates, the VA LCD has a low viewing-angle.
To improve the low viewing-angle of the VA LCD, an in-plane switching mode (IPS) LCD has been employed.
FIG. 1 is a cross-sectional view of an IPS LCD according to the related art.
In FIG. 1, an IPS LCD includes a color filter substrate 10, an array substrate 20, and a liquid crystal material layer 30 interposed between the two substrates 10 and 20.
Since a common electrode 52 and a pixel electrode 62 are disposed in the array substrate 20, a voltage supplied to each of the electrodes induces an in-plane electric field 26 to the liquid crystal material layer 30.
FIGS. 2A and 2B are cross-sectional views of off and on-states of an IPS LCD according to the related art, respectively.
In FIG. 2A, when an IPS LCD has an off-state, each of a common electrode 52 and a pixel electrode 62 is not supplied with a voltage, and thus an in-plane electric field is not induced. Accordingly, alignment of a liquid crystal molecule 32 is not changed, but remains to be directed along a rubbing direction R. The rubbing direction R has an angle of about 10 to 20 with the common electrode 52 or the pixel electrode 62.
In FIG. 2B, when the IPS LCD has an on-state, each of the common electrode 52 and the pixel electrode 62 is supplied with a voltage, and thus the in-plane electric field 26 is induced. The in-plane electric field 26 is induced between the common electrode 52 and the pixel electrode 62. Accordingly, alignment of the liquid crystal molecules 32a over the common electrode 52 and the pixel electrode 62 is not changed, and alignment of the liquid crystal molecules 32b between the common electrode 52 and the pixel electrode 62 is changed to the induced in-plane electric field 26.
In the IPS LCD, alignment of the liquid crystal molecules is changed depending on the in-plane electric field. Accordingly, the IPS LCD has a high viewing-angle.
FIG. 3 is a plan view of an array substrate for an IPS LCD according to the related art.
In FIG. 3, in an array substrate, a gate line 60 and a data line 70 cross each other to define a pixel region P, and a thin film transistor Tr is disposed at the crossing of the gate and data lines 60 and 70. A common line 80 is apart from the gate line 60, and a common electrode 85 is connected with the common line 80. A pixel electrode 95 is connected with the thin film transistor Tr, and is disposed between the adjacent common electrodes 85.
FIGS. 4 and 5 are cross-sectional views taken along lines A-A and B-B of FIG. 3, respectively.
In FIGS. 4 and 5, a gate line 60 (in FIG. 3), a gate electrode 61, a common line 80 (in FIG. 3) and a common electrode 85 are disposed on a substrate 57. A gate insulating layer 62 is disposed on the substrate 57 having the gate electrode 61. A semiconductor pattern 64 is disposed on the gate insulating layer 62 in a thin film transistor Tr, and includes an active layer 64a and an ohmic contact layer 64b, which are made of intrinsic amorphous silicon and doped amorphous silicon, respectively. A source electrode 66 and a drain electrode 68 are disposed on the semiconductor pattern 64, and a data line 70 is disposed on the gate insulating layer 62. A passivation layer 76 having a drain contact hole 77 is disposed on the substrate 57 having the source and drain electrodes 66 and 68. A pixel electrode 95 is disposed on the passivation layer 76, and contacts the drain electrode 68 through the drain contact hole 77.
In the related art IPS LCD, a voltage applied to the data line may interfere with a voltage applied to the pixel electrode. Accordingly, there is difference of transmissivities of a white color and a gray color, and thus cross-talk phenomenon occurs.
To minimize cross-talk phenomenon, the common electrode adjacent to the data line has a width of about 10 um, and the common line is disposed apart from the gate line with a predetermined space. As such, the common electrode and the common line occupy a large portion of the pixel region. Accordingly, in the related art IPS LCD, aperture ratio and brightness are reduced.